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DSPs are divided into two broad categories: fixed-point and floating-point. In general, the cutting-edge fixed-point families tend to be fast, low power, and low cost, while floating-point processors offer high precision and wide dynamic range.

Designers whose applications require only minimal amounts of floating-point functionality are caught in a "gray zone," often forced to move to higher-cost floating-point devices. Today, however, fixed-point processors are running at clock speeds that are high enough to emulate floating-point operations. This allows the designer to trade off floating-point computational efficiency for low cost and low power. This approach will not work for a truly float-intensive application, but it presents an appealing opportunity for designers "stuck in the gray zone."

Figure 1: The choice between a fixed-point and floating-point DSP isn't always clear  (click image to enlarge)

When representing fixed-point numbers, the radix point location depends on whether fractional math or integer math is used. While this convention simplifies numeric operations and conserves memory, it presents a tradeoff between dynamic range and precision. In situations that require both large dynamic range and high resolution, a radix point that can shift based on magnitude is desirable.

Very large and very small numbers can be stored in floating-point format, which consists of an exponent and mantissa. Each part of the floating-point number is stored in a fixed-point format. A floating-point number is normalized if it contains no redundant sign bits, meaning that all bits are significant. Normalization provides the highest precision for the number of bits available. It also simplifies the comparison of magnitudes, because the number with the greater exponent has the greater magnitude; only if the exponents are equal is it necessary to compare the fractions. Most routines assume normalized input and produce normalized results. Depending on whether dynamic range or precision is more important for a given application, floating-point emulation on a fixed-point DSP might use full IEEE-754 or non-IEEE-compliant formats. In some cases, even double-precision fixed-point math may suffice.

Figure 2: Floating-point emulation techniques on a 16-bit DSP (Path of arrows denotes decreasing core cycles required)  (click image to enlarge)

In 32-bit IEEE-754 format, a number can be formed as follows: Bit 31 (MSB) is the sign bit, bits 30 through 23 represent the exponent, and bits 22 through 0 represent the fractional mantissa. With an 8-bit exponent and a 23-bit mantissa, IEEE-754 reaches a balance between dynamic range and precision. IEEE floating-point libraries also include support for .features such as ± infinity, 0, and NaN (not a number).. On the Blackfin 16-bit fixed-point DSP, IEEE-754 floating-point functions are available as library calls from either C/C++ or assembly language. These libraries emulate floating-point processing using fixed-point logic. To reduce computational complexity, it is sometimes advantageous to use a modified version of IEEE-754. A cycle savings of over 10x can often be achieved in this way.

The Blackfin register file consists of sixteen 16-bit registers that can also be used as eight 32-bit registers. Two computation units, data registers that can be used with 32-bit data, and a full set of instructions that support arithmetic and logical operations allow floating-point emulation, non-IEEE formats, and multi-precision fixed point with greatly reduced computational requirements. To make optimal use of the Blackfin register file, floating-point emulation routines can use a two-word format, which provides one 16-bit word for the exponent and one for the fraction. Both words use signed two's-complement notation.

In addition to the combination of 16-bit and 32-bit data registers, the Blackfin architecture has dedicated instructions that facilitate efficient implementation of floating-point mathematics: SIGNBITS returns the number of sign bits in a number, which can then be passed to ASHIFT, which shifts the radix point to normalize the mantissa.

A fixed-point number can be converted to floating point by determining the number of sign bits and normalizing the mantissa through shifting it by that number. A floating-point number can be converted to fixed point by shifting the binary point of the mantissa by the appropriate number of sign bits.

Adding two numbers in floating-point format can be implemented as follows: 1. Set the exponent of the result to the larger of the two exponents. 2. Shift the mantissa of the smaller number to the right by the difference between the exponents. 3. Add the mantissas to produce the fraction of the result. 4. Normalize the result. Multiplication of two numbers in floating-point format is simpler than addition because there is no need to align the radix points. The algorithm can be implemented as follows: 1. Add the exponents. 2. Multiply the mantissas to produce the fraction of the result. 3. Normalize the result.

The floating-point multiply/accumulate routine computes the sum of N two-operand products. This can be performed using repeated calls to the floating-point multiplication and addition routines, but the multiply/accumulate routine functions more efficiently because it removes overhead. The multiply/accumulate algorithm can be implemented as follows: 1. Multiply the first two operands and normalize the product 2. Multiply the next two operands and normalize the product 3. Compare the product to the accumulated result, and shift one or the other to align the radix points 4. Add the product to the accumulated result and normalize the sum 5. Repeat steps 2 to 4 until all input operands are exhausted.

There are many applications where 16-bit fixed-point data is not sufficient, but emulating floating-point arithmetic may be too computationally intensive. For these applications, extended-precision fixed-point emulation may be enough to satisfy system requirements. Use of high-speed fixed-point DSPs will insure a significant reduction in the amount of required processing. Extended-precision numbers are represented in 31- or 32-bit fixed-point formats.

32-bit arithmetic is a natural software extension for 16-bit fixed-point processors. For processors whose 32-bit register files can be accessed as two 16-bit halves, these can be used together to represent a single 32-bit fixed-point number. Blackfin's hardware implementation allows for single-cycle 32-bit addition; 32-bit multiplication can be performed in a single instruction that takes five cycles. When a 32-bit multiply will be iterated with accumulation, Blackfin can achieve 32-bit accuracy with 16-bit multiplications in just three cycles.

31-bit accurate multiplications require only two cycles. This technique is especially appealing for high-end audio systems, which usually require at least 24-bit precision. Using the 6-dB-per-bit rule, 16-bit recordings are capable of a 96-dB dynamic range, while 24-bit fixed-point arithmetic improves the dynamic range to 144 dB.

Multiplication of the least significant half-word does not contribute much to the final result. In fact, if the result is truncated to 1.31, then this multiplication can only affect the least significant bit of the result. For many applications, this loss of accuracy is balanced by speeding up the 32-bit multiplication by eliminating one 16-bit multiplication, one shift, and one addition.

Today's fixed-point processors are entering a performance realm where they can satisfy some floating-point needs without requiring a floating-point processor. Choosing among floating-point and extended-precision fixed-point allows designers to balance dynamic range and precision on an as-needed basis, thus giving them a new level of control over DSP system implementations.