基本概念：
Cache memory takes advantage of locality by holding current data or program accesses closer
to the processor. The smallest block of data that the cache operates on is called a line.

Typically,the line size is larger than one data value or one instruction word in length.

If data from a requested memory location appears in a line of cache, this is called a hit. The
opposite event, a miss, occurs when the requested data is not found in the cache. If a miss
occurs, the next level of memory is accessed to fetch the missing data. The number of cache
misses is often an important measure of cache performance; the more misses you have, the lower

your performance will be. In addition when data is missed, a location needs to be selected
to place the newly cached data. This process is known as allocation, which often involves
replacing the data occupying an existing cache line to make room for the new data.

Cache的line放置策略：
Cache can be categorized by the schemes used for placing lines. A direct-mapped cache maps each

line of memory to exactly one location in the cache. This is in contrast to a multi-way set-

associative cache, which selects a “set” of locations to place the line. The number of
locations in each set is referred as the number of ways. For instance, in a 2-way set-associative

cache, each set consists of 2 line-frames (ways). Any given cacheable address in the memory map

maps to a unique set in the cache, and a line can be placed in two possible locations of that

set. An extreme of set-associative cache is fully associative cache that allows any memory

address to be stored at any location within the cache. For the latter two types of cache, an

allocation policy will be needed to choose among line frames in a set when a cache miss occurs.

Cache miss分类及避免：
Let us now investigate the sources of cache misses and how the misses can be remedied from the

programmer’s perspective. All cache misses can be divided into one of these three classes:

• Compulsory misses: these cache misses occur during the first access to a line. This miss
occurs because there was no prior opportunity for the data to be allocated in the cache.
These are sometimes referred to as ”first-reference misses”.
• Capacity misses: these cache misses occur when the cache does not have sufficient room to
hold all the data during the execution of a program.
• Conflict misses: these cache misses occur because more than one data or program code
are competing for the same cache line.

These sources of misses can be reduced by a number of code optimization techniques. Conflict
misses can be eliminated by changing the locations of data or program code in memory, and
hence they will not contend for the same cache line. Capacity misses can be reduced by
working on smaller amounts of data or code at a time, which can be achieved by reordering the
accesses of the data or by partitioning the algorithm into smaller pieces. Refer to TMS320C6000
DSP Cache User’s Guide (SPRU656) for more discussions on cache optimization techniques.

C6000 cache结构
the C6x1x CPU interfaces directly to a dedicated level-one program (L1P) and data (L1D) cache.
These L1 caches operate at the same speed as the CPU.
The L1P operates as a direct-mapped cache. It is readable only. The L1D is a two-way set
associative cache. The L1 memories are connected to a second-level memory of on-chip
memory called L2. L2 is a unified memory block that contains both program and data. The L2
cache serves as a bridge between the L1 and off-chip memory.