BF533 EZ-KIT DMA Config汇编源代码

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BF533 EZ-KIT DMA Config汇编源代码

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BF533 EZ-KIT DMA Config汇编源代码

作者：61IC 文章来源：本站原创点击数：更新时间：2007-1-22

/******************************************************************************/
//
// Name: BF533 EZ-KIT video ITU-656 receive mode (8bit) for the Omnivision chip OV6630
//
/******************************************************************************

File Name: BF533_EZ-KIT_DMA_Config.asm

Date Modified: 08/12/05 TL Rev 1.0

Software: VisualDSP++4.0, Assembler 2.6.7.5, Linker 3.5.2.2

Hardware: BF533 EZ-KIT Board (rev 1.7), Blackfin EZ-Extender (rev 1.2)

Chip: ADSP-BF533 REV 0.4

Special Connections: None

Purpose:    DMA controller setup


Program Parameters:

******************************************************************************************/
#include <defBF533.h>

/*****************************************************************************************/
// Global and extern subroutines
/*****************************************************************************************/

.global  BF533_EZ_KIT_DMA_Receive_Config;
.extern  Field1_First_Start_Address;
.extern  Field1_Second_Start_Address;

/*****************************************************************************************/
// Program Define Section
/*****************************************************************************************/
#define RAM_Length 0xFFFF
#define XCOUNT 0x06B4
#define XMOD 0x0001
#define YCOUNT 0x020D
#define YMOD 0x0001
#define DMA_Final_Transmit_Length 0x6FCC

/*****************************************************************************************/
// Program Variable Section
/*****************************************************************************************/
.section L1_data_a;

// descriptor setup
.align 4;
.byte2 DMA0_Receive_Descriptor_1[8];
.byte2 DMA0_Receive_Descriptor_2[8];
.byte2 DMA0_Receive_Descriptor_3[8];
.byte2 DMA0_Receive_Descriptor_4[8];
.byte2 DMA0_Receive_Descriptor_5[8];
.byte2 DMA0_Receive_Descriptor_6[8];
.byte2 DMA0_Receive_Descriptor_7[8];
.byte2 DMA0_Receive_Descriptor_8[8];
.byte2 DMA0_Receive_Descriptor_9[8];
.byte2 DMA0_Receive_Descriptor_10[8];
.byte2 DMA0_Receive_Descriptor_END = 0;

/*****************************************************************************************/
// Program
/*****************************************************************************************/
.section L1_code;

BF533_EZ_KIT_DMA_Receive_Config:

// Before the descriptor based DMA can run the DMA registers must be written first.

// Base pointer setup
p0.h = hi(DMA0_NEXT_DESC_PTR);
p0.l = lo(DMA0_NEXT_DESC_PTR);

// Write the first descriptors in the DMA descriptor registers
r0.h = DMA0_Receive_Descriptor_1;
r0.l = DMA0_Receive_Descriptor_1;
[p0] = r0;

// Target address of the DMA SDRAM = 0x0
r0.h = 0x0;
r0.l = 0x0;
[p0+DMA0_START_ADDR-DMA0_NEXT_DESC_PTR] = r0;

// RAM_Length 32bit trasnfers will be executed
r0 = RAM_Length(z);
w[p0+DMA0_X_COUNT-DMA0_NEXT_DESC_PTR] = r0;

// The modifier is set to 4 because of the 32bit transfers
r0 = 4(z);
w[p0+DMA0_X_MODIFY-DMA0_NEXT_DESC_PTR] = r0;

//PPI Peripheral is used
r0 = 0x0000(z);
w[p0+DMA0_PERIPHERAL_MAP-DMA0_NEXT_DESC_PTR] = r0;

//large descriptor model; 7 descriptor elements; interrupt; interrupt after completion;
// retain FIFO; linear DMA; 32 bit transfer; DMA still disabled
r0 = 0x770A (z);
w[p0+DMA0_CONFIG-DMA0_NEXT_DESC_PTR] = r0;
SSYNC;

/*******************************************************************************/

// Each descriptor includes the following order and contents:

// Next descriptor address  32bit wide
// Target address    32bit wide
// DMA config register   16bit wide
// XCount register    16bit wide
// XModifier register   16bit wide

//DMA Descriptor 1
p0.l = DMA0_Receive_Descriptor_1;
p0.h = DMA0_Receive_Descriptor_1;
R0.l = DMA0_Receive_Descriptor_2;
R0.h = DMA0_Receive_Descriptor_2;
[p0]= r0;
r0 = 0;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 2
p0.l = DMA0_Receive_Descriptor_2;
p0.h = DMA0_Receive_Descriptor_2;
R0.l = DMA0_Receive_Descriptor_3;
R0.h = DMA0_Receive_Descriptor_3;
[p0]= r0;
r0.h = 0x0003;
r0.l = 0xfffc;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 3
p0.l = DMA0_Receive_Descriptor_3;
p0.h = DMA0_Receive_Descriptor_3;
R0.l = DMA0_Receive_Descriptor_4;
R0.h = DMA0_Receive_Descriptor_4;
[p0]= r0;
r0.h = 0x0007;
r0.l = 0xFFF8;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 4
p0.l = DMA0_Receive_Descriptor_4;
p0.h = DMA0_Receive_Descriptor_4;
R0.l = DMA0_Receive_Descriptor_5;
R0.h = DMA0_Receive_Descriptor_5;
[p0]= r0;
r0.h = 0x000B;
r0.l = 0xFFF4;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 5
p0.l = DMA0_Receive_Descriptor_5;
p0.h = DMA0_Receive_Descriptor_5;
R0.l = DMA0_Receive_Descriptor_6;
R0.h = DMA0_Receive_Descriptor_6;
[p0]= r0;
r0.h = 0x000F;
r0.l = 0xFFF0;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 6
p0.l = DMA0_Receive_Descriptor_6;
p0.h = DMA0_Receive_Descriptor_6;
R0.l = DMA0_Receive_Descriptor_7;
R0.h = DMA0_Receive_Descriptor_7;
[p0]= r0;
r0.h = 0x0013;
r0.l = 0xFFEC;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 7
p0.l = DMA0_Receive_Descriptor_7;
p0.h = DMA0_Receive_Descriptor_7;
R0.l = DMA0_Receive_Descriptor_8;
R0.h = DMA0_Receive_Descriptor_8;
[p0]= r0;
r0.h = 0x0017;
r0.l = 0xFFE8;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 8
p0.l = DMA0_Receive_Descriptor_8;
p0.h = DMA0_Receive_Descriptor_8;
R0.l = DMA0_Receive_Descriptor_9;
R0.h = DMA0_Receive_Descriptor_9;
[p0]= r0;
r0.h = 0x001B;
r0.l = 0xFFE4;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 9
p0.l = DMA0_Receive_Descriptor_9;
p0.h = DMA0_Receive_Descriptor_9;
R0.l = DMA0_Receive_Descriptor_10;
R0.h = DMA0_Receive_Descriptor_10;
[p0]= r0;
r0.h = 0x001F;
r0.l = 0xFFE0;
[p0 + 4] = r0;
r0 = 0x770B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

//DMA Descriptor 10
p0.l = DMA0_Receive_Descriptor_10;
p0.h = DMA0_Receive_Descriptor_10;
R0.l = DMA0_Receive_Descriptor_END;
R0.h = DMA0_Receive_Descriptor_END;
[p0]= r0;
r0.h = 0x0023;
r0.l = 0xFFDC;
[p0 + 4] = r0;
r0 = 0x778B(z);
w[p0 + 8] = r0;
r0 = RAM_Length(z);
w[p0 + 10] = r0;
r0 = 4(z);
w[p0 + 12] = r0;

/*******************************************************************************/

//Enable DMA
p0.h = hi(DMA0_CONFIG);
p0.l = lo(DMA0_CONFIG);
r0.l = w[p0];
bitset(r0,0);
w[p0] = r0.l;
ssync;

BF533_EZ_KIT_DMA_Receive_Config.END:
RTS;
/*******************************************************************************/

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