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TMS320F2812模块配置的初始化程序，已经通过实际产品的测试并应用
//
// TMDX ALPHA RELEASE
// Intended for product evaluation purposes
//
//###########################################################################
//
// FILE: DSP28_ECan.c
//
// TITLE: DSP28 Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
// 0.56| 20 May 2002 | L.H. | No change
// 0.57| 27 May 2002 | L.H. | No change
// 0.58| 29 Jun 2002 | L.H. | No change
// 1.0 | 23 Otc 2004 | CY.L.| Added several initialization routines
//###########################################################################
#include "DSP28_Device.h"
//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
#define MSGID MID
void InitECan(void)
{
struct ECAN_REGS ECanaShadow;
Uint32 MBOXMID;
Uint16 BRP;
EALLOW;
GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
/* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/
ECanaRegs.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANRIOC.bit.RXFUNC = 1;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaRegs.CANMC.bit.SCB = 1; //0--SCC mode; 1-eCAN mode.
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MCF register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MCF must be initialized to zero
ECanaMboxes.MBOX0.MCF.all = 0x00000000;
ECanaMboxes.MBOX1.MCF.all = 0x00000000;
ECanaMboxes.MBOX2.MCF.all = 0x00000000;
ECanaMboxes.MBOX3.MCF.all = 0x00000000;
ECanaMboxes.MBOX4.MCF.all = 0x00000000;
ECanaMboxes.MBOX5.MCF.all = 0x00000000;
ECanaMboxes.MBOX6.MCF.all = 0x00000000;
ECanaMboxes.MBOX7.MCF.all = 0x00000000;
ECanaMboxes.MBOX8.MCF.all = 0x00000000;
ECanaMboxes.MBOX9.MCF.all = 0x00000000;
ECanaMboxes.MBOX10.MCF.all = 0x00000000;
ECanaMboxes.MBOX11.MCF.all = 0x00000000;
ECanaMboxes.MBOX12.MCF.all = 0x00000000;
ECanaMboxes.MBOX13.MCF.all = 0x00000000;
ECanaMboxes.MBOX14.MCF.all = 0x00000000;
ECanaMboxes.MBOX15.MCF.all = 0x00000000;
ECanaMboxes.MBOX16.MCF.all = 0x00000000;
ECanaMboxes.MBOX17.MCF.all = 0x00000000;
ECanaMboxes.MBOX18.MCF.all = 0x00000000;
ECanaMboxes.MBOX19.MCF.all = 0x00000000;
ECanaMboxes.MBOX20.MCF.all = 0x00000000;
ECanaMboxes.MBOX21.MCF.all = 0x00000000;
ECanaMboxes.MBOX22.MCF.all = 0x00000000;
ECanaMboxes.MBOX23.MCF.all = 0x00000000;
ECanaMboxes.MBOX24.MCF.all = 0x00000000;
ECanaMboxes.MBOX25.MCF.all = 0x00000000;
ECanaMboxes.MBOX26.MCF.all = 0x00000000;
ECanaMboxes.MBOX27.MCF.all = 0x00000000;
ECanaMboxes.MBOX28.MCF.all = 0x00000000;
ECanaMboxes.MBOX29.MCF.all = 0x00000000;
ECanaMboxes.MBOX30.MCF.all = 0x00000000;
ECanaMboxes.MBOX31.MCF.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
/* Clear all TAn bits */
ECanaRegs.CANTA.all = 0xFFFFFFFF;
/* Clear all RMPn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF;
/* Clear all interrupt flag bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters */
ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1
while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
ECanaRegs.CANBTC.bit.TSEG2 = 2;
ECanaRegs.CANBTC.bit.TSEG1 = 10;
/* //150M
switch(CanBaudrate)
{
case 0 : BRP=9; break; //1M
case 1 : BRP=19; break; //500k
case 2 : BRP=39; break; //250k
case 3 : BRP=79; break; //125k
case 4 : BRP=99; break; //100k
case 5 : BRP=110; break; //90k
case 6 : BRP=124; break; //80k
case 7 : BRP=142; break; //70k
case 8 : BRP=166; break; //60k
case 9 : BRP=199; break; //50k
case 10 : BRP=249; break; //40k
default : BRP=249; break; //40k
}
*/
/* //120M
switch(CanBaudrate)
{
case 0 : BRP=1000; break; //1M
case 1 : BRP=500; break; //500k
case 2 : BRP=250; break; //250k
case 3 : BRP=125; break; //125k
case 4 : BRP=100; break; //100k
case 5 : BRP=90; break; //90k
case 6 : BRP=80; break; //80k
case 7 : BRP=70; break; //70k
case 8 : BRP=60; break; //60k
case 9 : BRP=50; break; //50k
case 10 : BRP=40; break; //40k
default : BRP=40; break; //40k
}
BRP=SYSCLK/(15*1000*BRP)-1;
*/
// sysclk=120M
switch(CanBaudrate)
{
case 10 : BRP=7; break; //1M
case 9 : BRP=15; break; //500k
case 8 : BRP=31; break; //250k
case 7 : BRP=63; break; //125k
case 6 : BRP=79; break; //100k
case 5 : BRP=88; break; //90k
case 4 : BRP=99; break; //80k
case 3 : BRP=113; break; //70k
case 2 : BRP=132; break; //60k
case 1 : BRP=159; break; //50k
case 0 : BRP=199; break; //40k
default : BRP=199; break; //40k
}
ECanaRegs.CANBTC.bit.BRP=BRP;
ECanaRegs.CANMC.bit.STM = 0; // Configure CAN for no self-test mode
ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0
while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
ECanaRegs.CANGAM.bit.AMI=1;
ECanaRegs.CANGAM.bit.GAM2816=0x0007; //not used by eCAN mode
// Configure Mailboxe6 as Receive mailboxes
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD6=1;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
// ID bit28~21 as Unit ID, bit20~18 as frame information:
// 80--single frame, E0--first frame of multi frame
// A0--middle frame of multi frame
// C0--last frame of multi frame
MBOXMID=((Uint32)ComAddr)<<21;
MBOXMID=MBOXMID|0x40000000;
ECanaMboxes.MBOX6.MSGID.all=MBOXMID; // Std identifier include Unit addr
ECanaLAMRegs.LAM6.all=0x001C0000; // mask bit20~18
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME6 =1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
// Configure Mailboxe4 as Receive mailboxes
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD4=1;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
// ID bit28~21 as Unit ID, bit20~18 as frame information:
// 80--single frame, E0--first frame of multi frame
// A0--middle frame of multi frame
// C0--last frame of multi frame
MBOXMID=((Uint32)MasterAddr)<<21;
MBOXMID=MBOXMID|0x40000000;
ECanaMboxes.MBOX4.MSGID.all=MBOXMID; // Std identifier include Unit addr
ECanaLAMRegs.LAM4.all=0x001C0000; // mask bit20~18
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME4 =1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
/* Configure Mailbox5 as a Transmit mailbox */
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD5 = 0;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
MBOXMID=((Uint32)ComAddr)<<21;
MBOXMID=MBOXMID|0x40000000;
ECanaMboxes.MBOX5.MID.all=MBOXMID; // Std Identifier
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME5 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
ECanaShadow.CANMIL.all = 0xFFFFFFFF ; // Interrupts asserted on eCAN1INT
ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;
ECanaShadow.CANMIM.all = 0x00000070; // Enable interrupts for 4,5,6 mailboxes
ECanaRegs.CANMIM.all = ECanaShadow.CANMIM.all;
ECanaShadow.CANGIM.all = 0;
ECanaShadow.CANGIM.bit.I1EN = 1;
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
EDIS;
PieCtrlRegs.PIECRTL.bit.ENPIE = 1; // Enable vector fetching from PIE block
PieCtrlRegs.PIEACK.bit.ACK9 = 1; // Enables PIE to drive a pulse into the CPU
// The interrupt can be asserted in either of the eCAN interrupt lines
// Comment out the unwanted line...
PieCtrlRegs.PIEIER9.bit.INTx5 = 0; // Enable INTx.5 of INT9 (eCAN0INT)
PieCtrlRegs.PIEIER9.bit.INTx6 = 1; // Enable INTx.6 of INT9 (eCAN1INT)
/* Configure system interrupts */
IER |= M_INT9; // Enable INT9 of CPU
}
/***************************************************/
/* Bit configuration parameters for 150 MHz SYSCLKOUT*/
/***************************************************/
/*
The table below shows how BRP field must be changed to achieve different bit
rates with a BT of 15, for a 80% SP:
---------------------------------------------------
BT = 15, TSEG1 = 10, TSEG2 = 2, Sampling Point = 80%
---------------------------------------------------
1 Mbps : BRP+1 = 10 : CAN clock = 15 MHz
500 kbps : BRP+1 = 20 : CAN clock = 7.5 MHz
250 kbps : BRP+1 = 40 : CAN clock = 3.75 MHz
125 kbps : BRP+1 = 80 : CAN clock = 1.875 MHz
100 kbps : BRP+1 = 100 : CAN clock = 1.5 MHz
50 kbps : BRP+1 = 200 : CAN clock = 0.75 MHz
90 kbps : BRP+1 = 111
80 kbps : BRP+1 = 125
70 kbps : BRP+1 = 143
60 kbps : BRP+1 = 167
50 kbps : BRP+1 = 200
40 kbps : BRP+1 = 250
*/
/***************************************************/
/* Bit configuration parameters for 120 MHz SYSCLKOUT*/
/***************************************************/
/*
The table below shows how BRP field must be changed to achieve different bit
rates with a BT of 15, for a 80% SP:
---------------------------------------------------
BT = 15, TSEG1 = 10, TSEG2 = 2, Sampling Point = 80%
---------------------------------------------------
1 Mbps : BRP+1 = 8 : CAN clock = 15 MHz
500 kbps : BRP+1 = 16 : CAN clock = 7.5 MHz
250 kbps : BRP+1 = 32 : CAN clock = 3.75 MHz
125 kbps : BRP+1 = 64 : CAN clock = 1.875 MHz
100 kbps : BRP+1 = 80 : CAN clock = 1.5 MHz
50 kbps : BRP+1 = 160 : CAN clock = 0.75 MHz
90 kbps : BRP+1 = 89
80 kbps : BRP+1 = 100
70 kbps : BRP+1 = 114
60 kbps : BRP+1 = 133
50 kbps : BRP+1 = 160
40 kbps : BRP+1 = 200
*/
//===========================================================================
// No more.
//===========================================================================
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