程序1：
type clock_type is (s0，s1，s2，s3);
signal state0:clock_type;
signal state1:state_type;
case state is
        when s0=>
          da<='1';
          scl<='1';
          state<=s1;
        when s1=>
          da<='1';
          scl<='1';
          state<=s2;
        when s2=>
          da<='0';
          scl<='1';
          state<=s3;
        when s3=>
          da<='0';
          scl<='0';
          state<=s0;
          state1<=s_byte;
        when others=>
          state<=s0;
       end case;

下面是利用case…when语句编写的移位及输入、输出字节模块。
inoutdata:block
 signal code:std_logic_vector(2 downto 0);
 begin
process(read，endata，cl)   --cl与scl同步
begin
  code<=read & endata & flag;
  if cl'event and cl='1'then
   case code is          
     when "010"|"011" =>   --从MCU读入一个要发送的数据
        datain<=data;
     when "001"=>        --8位左移寄存器，将要输出的位存于data7
        data7<=datain(7);
        datain(0)<='1';
        for i in 1 to 7 loop
         datain(i)<=datain(i-1);
        end loop;
     when "101"=>        --将向MCU发送的数据暂存于dataout
        dataout<=data1;
     when "100"=>        --8位右移寄存器，data0为从SDA接收的值
        data1(0)<=data0;
        for i in 1 to 7 loop
         data1(i)<=data1(i-1);
        end loop;
     when others=>
        null;
   end case;
  end if;
end process;
end block inoutdata;