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第二章、组合逻辑电路
1、监视交通信号工作状态的逻辑电路
library ieee;
use ieee.std_logic_1164.all;
entity hld is
port(r,a,g:in std_login;
z:out std_logic);
end hld;
architecture rtl of hld is
begin
process(r,a,g)
variable conb:std_logic_vector(2 downto 0);
begin
comb:=r&a&g;
case comb is
when"000"=>z<='1';
when"001"=>z<='0';
when"010"=>z<='0';
when"011"=>z<='1';
when"100"=>z<='0';
when"101"=>z<='1';
when"110"=>z<='1';
when others=>z<='1';
end case;
end process;
end rtl;
2、8线---3线编码器的设计
library ieee;
use ieee.std_logic_1164.all;
entity bm8_3 is
port(a:in std_logic_vector(7 downto 0);
b:out std_logic_vector(2 downto 0));
end bm8_3;
architecture rtl ofbm8_3 is
begin
process(a)
begin
case a is
when"00000001"=>b<="000";
when"00000010"=>b<="001";
when"00000100"=>b<="010";
when"00001000"=>b<="011";
when"00010000"=>b<="100";
when"00100000"=>b<="101";
when"01000000"=>b<="110";
when others=>b<="111";
end case;
end process;
end rtl;
3、8线---3线优先编码器的设计
library ieee;
use ieee.std_logic_1164.all;
entity yxbm8_3 is
port(i:in std_logic_vector(7 downto 0);
s:in std_logic;
y:out std_logic_vector(2 cownto 0);
ys,yex:out std_logic);
end yxbm8_3
architecture rtl of yxbm8_3 is
begin
process(i,s)
begin
if s='1'then
y<="111";
ys<='1';
ysx<='0';
else
if i(7)='0'then
y<="001";
ys<='1';
ysx<='0';
else
if i(6)='0'then
y<="001";
ys<='1';
ysx<='0';
else
if i(5)='0'then
y<="010";
ys<='1';
ysx<='0';
else
if i(4)='0'then
y<="011";
ys<='1';
ysx<='0';
else
if i(3)='0'then
y<="100";
ys<='1';
ysx<='0';
else
if i(2)='0'then
y<="101";
ys<='1';
ysx<='0';
else
if i(1)='0'then
y<="110";
ys<='1';
ysx<='0';
else
if i(0)='0'then
y<="111";
ys<='1';
ysx<='0';
else
if i='11111111'then
y<="111";
ys<='1';
ysx<='0';
end if;
end if;
end process;
end rtl;
4、二---十进制编码器的设计
library ieee;
use ieee.std_logic_1164.all;
entity bmq is
port(i:in std_logic_vector(8 downto 0);
yLout std_logic_vctor(3 downto 0));
end bmq;
architecture rtl of bmq is
begin
process(i);
begin
if i(8)='0'then
y<="0110";
elsif i(7)='0'then
y<="0111";
elsif i(6)='0'then
y<="1000";
elsif i(5)='0'then
y<="1001";
elsif i(4)='0'then
y<="1010";
elsif i(3)='0'then
y<="1011";
elsif i(2)='0'then
y<="1100";
elsif i(1)='0'then
y<="1101";
elsif i(0)='0'then
y<="1110";
elsif i='11111111'then
y<="1111";
end if;
end process;
end rtl;
5、译码器（3线---8线）的设计
library ieee;
use ieee.std_logic_1164.all;
entity ym3_8 is
port(A0,A1,A2:in bit;
s1,s2,s3:in bit;
y0,y1,y2,y3,y4,y5,y6,y7:out bit);
end ym3_8;
architecture rtl of ym3_8 is
signal s:bit;
signal A:bit_vector(2 downto 0);
signal y:bit_vector(7 downto 0);
begin
process(A,s1,s2,s3)
begin
s<=s2 or s3;
A<=A2&A1&A0;
if s1='0'then
y<="11111111"
elsif s='1'then
y<="11111111";
else
case A is
when"000"=>y<="11111110";
when"001"=>y<="11111101";
when"010"=>y<="11111011";
when"011"=>y<="11110111";
when"100"=>y<="11101111";
when"101"=>y<="11011111";
when"110"=>y<="10111111";
when others=>y<="01111111";
end case;
end if;
end process;
y0<=y(0);
y1<=y(1);
y2<=y(2);
y3<=y(3);
y4<=y(4);
y5<=y(5);
y6<=y(6);
y7<=y(7);
end rtl;
6、二---十进制译码器的设计
library ieee;
use ieee.std_logic_1164.all;
entity ym2_10 is
port(a:in atd_logic_vector(3 downto 0);
y:out atd_logic_vector(9 downto 0));
end ym2_10:
architecture rtl of ym2_10 is
bigin
process(a)
bigin
case a is
when"0000"=>y<="1111111110";
when"0001"=>y<="1111111101";
when"0010"=>y<="1111111011";
when"0011"=>y<="1111110111";
when"0100"=>y<="1111101111";
when"0101"=>y<="1111011111";
when"0110"=>y<="1110111111";
when"0111"=>y<="1101111111";
when"1000"=>y<="1011111111";
when"1001"=>y<="0111111111";
when pthers=>y<="11111111";
end case;
end process;
end rtl;
7、BCD七段显示译码器的设计
library ieee;
use ieee.std_logic_1164.all;
entity qdym is
port(a:in atd_logic_vector(3 downto 0);
y:out atd_logic_vector(6 downto 0));
end qdym;
architecture rtl of qdym is
begin
process(a)
begin
case a is
when"0000"=>Y<="0111111";
when"0001"=>Y<="0000110";
when"0010"=>Y<="1011011";
when"0011"=>Y<="1001111";
when"0100"=>Y<="1100110";
when"0101"=>Y<="1101101";
when"0110"=>Y<="1111101";
when"0111"=>Y<="0100111";
when"1000"=>Y<="1111111";
when"1001"=>Y<="1101111";
when"1010"=>Y<="1110111";
when"1011"=>Y<="1111100";
when"1100"=>Y<="0111001";
when"1101"=>Y<="1011110";
when"1110"=>Y<="1111001";
when OTHERS=>Y<="1110001";
end case;
end process;
end rtl;
8、代码转换
library ieee;
use ieee.std_logic_1164.all;
entity zhuanhuan is
port(x0,x1,x2,x3:in std_logic;
c:in std_logic;
y0,y1,y2,y3:out std_logic);
end zhuanhuan;
architecture rtl of zhuanhuan is
begin
y3<=x3;
y2<=(x3 and(not x2))or((not x3)and x2);
y1<=((not c)and((x3 and x2 and x1)or((not x3)and(not x2)andx1)or((not x3)and x2 and(not
x1))or(x3 and(out x2)and(out x1))))or(c and((x2 and(notx1))or((not x2)and x1)));
y0<=((not c)and(((not x3)and(not x2)and(not x1)and x0)or((not x3)and(not x2)and(not x0)
and x1)or((notand(not x0)and(not x1)and x2)or((not x3)and x2 and x1 and x0)or(x3 and x2 and
(not x1)and x0)or((not x0)and x2 and x1 and x3)or((not x0)and(not x2)and(not x1)and x3)0r(x3
and(not x2)and x1 and x0)))or(c and((x1 and(not x0))or((not x1)and x0)));
end rtl;
9、四选一数据选择器的设计
library ieee;
use ieee.std_logic_1164.all;
entity cxy is
port(d0,d1,d2,d3,a0,a1,s:in std_logic;
y:out std_logic);
end cxy;
architecture rtl of cxy is
signal a:std_logic_vector(1 downto 0);
begin
process(a0,a1)
begin
a<=a1&a0;
if(s='0')then
case a is
when"00"=>y<=d0;
when"01"=>y<=d1;
when"10"=>y<=d2;
when others=>y<=d3;
end case;
end if;
end process;
end rtl;
10、八选一数据选择器的设计
library ieee;
use ieee.std_logic_1164.all;
entity 1334 is
port(d0,d1,d2,d3,d4,d5,d6,d7,a0,a1,a2:in std_logic;
y:out std_logic);
end 1334;
architecture rtl of 1334 is
signal a:std_logic_vector(2 downto 0);
begin
process(a0,a1,a2)
begin
a<=a2&a1&a0;
case a is
when"000"=>y<=d0;
when"001"=>y<=d1;
when"010"=>y<=d2;
when"011"=>y<=d3;
when"100"=>y<=d4;
when"101"=>y<=d5;
when"110"=>y<=d6;
when others=>y<=d7;
end case;
end process;
end rtl;
11、4位全加器的设计
（1）1位全加器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qjq is
port(a,b:in std_logic;
ci:in std_logic;
co:out std_logic;
s:out std_logic);
end qjq;
architecture rtl of qjq is
begin
process(a,b,ci);
begin
if(a='0'and b='0'and ci='0')then
s<='0';
so<='0';
elsif(a='1'and b='0'and ci='0')then
s<='1';
so<='0';
elsif(a='0'and b='1'and ci='0')then
s<='1';
so<='0';
elsif(a='1'and b='1'and ci='0')then
s<='0';
so<='1';
elsif(a='0'and b='0'and ci='1')then
s<='1';
so<='0';
elsif(a='0'and b='1'and ci='1')then
s<='0';
so<='1';
elsif(a='1'and b='0'and ci='1')then
s<='0';
so<='1';
else
s<='1';
co<='1';
end if;
end process;
end rtl;
12、8位加法器的设计
程序一：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4b is
port (cin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end adder4b;
architecture behav of adder4b is
signal sint:std_logic_vector(4 downto 0);
signal aa:std_logic_vector(4 downto 0);
begin
aa<='0'&a(3 downto 0);
bb<='0'&b(3 downto 0);
sint<=aa+bb+cin;
s(3 downto 0)<=sint(3 downto 0);
cout<=sint(4)
end behav;
程序二：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder8b is
port (cin:in std_logic;
a,b:in std_logic_vector(7 downto 0);
s:out std_logic_vector(7 downto 0);
cout:out std_logic);
end adder8b;
architecture behav of adder8b is
component adder4b
port (cin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end component;
signal carry_out:std_logic;
begin
u1:adder4b port map(cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>(3 downto 0),
cout=>carry_out);
u2:adder4b port map(cin=>carry_out,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>cout);
end struc;
13、多位数值比较器的设计
library ieee;
use ieee.std_logic_1164.all;
entity cc14585 is
port(a,b:in std_logic_vector(3 downto 0);
cc14585y1,y2,y3:out std_logic);
end cc14585;
architecture rtl of cc14585 is
begin
process(a,b)
begin
if(a>b)then
y1<='1';
y2<='0';
y3<='0';
elsif(a=b)then
y1<='0';
y2<='1';
y3<='0';
else
y1<='0';
y2<='0';
y3<='1';
end if;
end process;
end rtl;
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