3。1。RS触发器的设计

library ieee;
use ieee.std_logic_1164.all;
entity rsff is
   port(r,s:in std_logic;
        q,qb:out std_logic);
end rsff;

architecture rtl of rsff is
signal q_temp,qb_tempLstd_logic;
begin
process(r,s)
begin
  if(s='1'and r='0')then
  q_temp<='0';
 qb_temp<='1';
 elsif(s='0'and r='1') then
 q_temp<='1';
qb_temp<='0';
else
q_temp<=q_temp;
  qb_temp<=qb_temp;
end if;
end process;
q<=q_temp;
qb<=qb_temp;
end rtl;

3。2主从JK触发器的设计

源程序：
library ieee;
use ieee.std_logic_1164.all;
  entity jkff is
  port(j,k,cp,r,s:in std_logic;
          q,pb:out std_logic);
end jkff;
architecture rtl of kff is
signal q_temp,qb_temp:std_logic;
begin
process(j,k,cp)
begin
if(r='0' and s='1')then
   q_temp<='0';
   qb_temp<='1';
elsif(r='1'and s='0')then
   q_temp<='1';
  qb_temp<='0';
elsif(cp'event and cp='0')then
   if(j='0' and k='1')then
      q_temp<=not q_temp;
     qb_temp<=not qb_temp;
  end if;
end if;

q<=q_temp;
qb<=qb_temp;
end process;
end rtl;

3。3，D触发器的设计

源程序：
 
library ieee;
usre ieee.std_logic)_1164.all;
 
entity dff is
  port(d,cp,r,s:in std_logic;
          q,qb:out std_logic);
 end dff;
architecture rtl of dff is
signal q_temp,qb_temp:std_logic;
begin
   process(cp)
   begin
if(r='0' and s='1')then
   q_temp<='0';
  qb_temp<='1';
elsif(r='1' and s='0')then
  q_temp<='1';
  qb_temp<='0';
elsif(r='0' and s='0')then
  q_temp<=q_temp;
 qb_temp<=qb_temp;
elsif(cp'event and cp='0')then
  q_temp<=d;
 qb_temp<=not d;
end if
end process;
q<=q_temp;
qb<=qb_temp;
end rtl;