//--------------------------------------------------------------------------------------------------

// File        : decoder3_8_TB.v

//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps

module decoder3_8_tb;

//Internal signals declarations:

reg G1;

wire [7:0]Y;

reg G2;

reg [2:0]A;

reg G3;

// Unit Under Test port map

 decoder3_8 UUT (

  .G1(G1),

  .Y(Y),

  .G2(G2),

  .A(A),

  .G3(G3));

// -- edit by liwei  -- //

initial

 begin

  G1 = 1;

  G2 = 1;

  G3 = 0;

 #100 A <= 3'b010;

 #100 G2 = 0;

 #100 A <= 3'b110;

 #100 A <= 3'b000;

 #100 A <= 3'b001;

 #100 A <= 3'b010;

 #100 A <= 3'b011;

 #100 G1 <= 0;

 #100 G1 <= 1;

 #100 A <= 3'b100;

 #100 A <= 3'b101;

 #100 A <= 3'b110;

 #100 A <= 3'b111;

 end

 //$monitor($realtime,,"ps %h %h %h %h %h ",G1,Y,G2,A,G3);

endmodule

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//-------------------------------------------------------------------------------------------------

// File        : decoder3_8.v

//-------------------------------------------------------------------------------------------------

`timescale 1 ns / 1 ps

//{{ Section below this comment is automatically maintained

//   and may be overwritten

//{module {decoder3_8}}

module decoder3_8 ( G1 ,Y ,G2 ,A ,G3 );

input G1 ;

wire G1 ;

input G2 ;

wire G2 ;

input [2:0] A ;

wire [2:0] A ;

input G3 ;

wire G3 ;

output [7:0] Y ;

reg [7:0] Y ;

reg s;

//}} End of automatically maintained section

// -- edit by liwei  -- //

always @ ( A ,G1, G2, G3)

 begin

  s <= G2 | G3 ;

  if ( G1 == 0)

   Y <= 8'b1111_1111;

  else if ( s)

   Y <= 8'b1111_1111;

  else

   case ( A )

    3'b000 : Y<= 8'b1111_1110;

    3'b001 : Y<= 8'b1111_1101;

    3'b010 : Y<= 8'b1111_1011;

    3'b011 : Y<= 8'b1111_0111;

    3'b100 : Y<= 8'b1110_1111;

    3'b101 : Y<= 8'b1101_1111;

    3'b110 : Y<= 8'b1011_1111;

    3'b111 : Y<= 8'b0111_1111;

   endcase

  end

endmodule

注意以下语句中，1和2之间的并列关系，时钟来临时1和2是同时执行的。当G1=1，G2=1,G3=0时，同时执行1和2的代码，执行1的结果是，s<=1；2只执行case（A）语句

 begin

1.  s <= G2 | G3 ;       

2.  if ( G1 == 0)

      Y <= 8'b1111_1111;

    else if ( s)

      Y <= 8'b1111_1111; 

    else

      case ( A )