//serial为serial input,control为paraller/serial control， P为两位并行输入，Q为两位输出
module shift(clk,serial,control,P,Q);
input clk,serial,control;
input [1:0] P;
output [1:0] Q;

reg [1:0] temp;  //temp 为寄存器，暂存串行输出数据

always @(control)  
begin
   if(control == 1'b1)
     Q = P;
   else
     Q = temp2;
end

always @(posedge clk)
begin
   if(control == 1'b0)
   begin
   temp[0] <= serial;
   temp[1] <= temp0;
   end   
   else
   begin
   temp <= temp;
   end
end