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Practical FPGA Programming in C

By David Pellerin, Scott Thibault

...............................................

Publisher: Prentice Hall PTR

Pub Date: April 22, 2005

ISBN: 0-13-154318-0

Pages: 464

     Copyright

     Prentice Hall Modern Semiconductor Design Series

     Foreword

        Why is this book of interest to the hardware folks?

        And what about the software guys and gals?

        So what's the catch?

     Preface

        C Language for FPGA-Based Hardware Design?

        Compelling Platforms for Software Acceleration

        The Power to Experiment

        How This Book Is Organized

        Where This Book Came From

     Acknowledgments

     Chapter 1.  The FPGA as a Computing Platform

        Section 1.1.  A Quick Introduction to FPGAs

        Section 1.2.  FPGA-Based Programmable Hardware Platforms

        Section 1.3.  Increasing Performance While Lowering Costs

        Section 1.4.  The Role of Tools

        Section 1.5.  The FPGA as an Embedded Software Platform

        Section 1.6.  The Importance of a Programming Abstraction

        Section 1.7.  When Is C Language Appropriate for FPGA Design?

        Section 1.8.  How to Use This Book

     Chapter 2.  A Brief History of Programmable Platforms

        Section 2.1.  The Origins of Programmable Logic

        Section 2.2.  Reprogrammability, HDLs, and the Rise of the FPGA

        Section 2.3.  Systems on a Programmable Chip

        Section 2.4.  FPGAs for Parallel Computing

        Section 2.5.  Summary

     Chapter 3.  A Programming Model for FPGA-Based Applications

        Section 3.1.  Parallel Processing Models

        Section 3.2.  FPGAs as Parallel Computing Machines

        Section 3.3.  Programming for Parallelism

        Section 3.4.  Communicating Process Programming Models

        Section 3.5.  The Impulse C Programming Model

        Section 3.6.  Summary

     Chapter 4.  An Introduction to Impulse C

        Section 4.1.  The Motivation Behind Impulse C

        Section 4.2.  The Impulse C Programming Model

        Section 4.3.  A Minimal Impulse C Program

        Section 4.4.  Processes Streams Signals, and Memory

        Section 4.5.  Impulse C Signed and Unsigned Datatypes

        Section 4.6.  Understanding Processes

        Section 4.7.  Understanding Streams

        Section 4.8.  Using Output Streams

        Section 4.9.  Using Input Streams

        Section 4.10.  Avoiding Stream Deadlocks

        Section 4.11.  Creading and Using Signals

        Section 4.12.  Understanting Registers

        Section 4.13.  Using Shared Memories

        Section 4.14.  Memory and Stream Performance Considerations

        Section 4.15.  Summary

     Chapter 5.  Describing a FIR Filter

        Section 5.1.  Design Overview

        Section 5.2.  The FIR Filter Hardware Process

        Section 5.3.  The Software Test Bench

        Section 5.4.  Desktop Simulation

        Section 5.5.  Application Monitoring

        Section 5.6.  Summary

     Chapter 6.  Generating FPGA Hardware

        Section 6.1.  The Hardware Generation Flow

        Section 6.2.  Understanding the Generated Structure

        Section 6.3.  Stream and Signal Interfaces

        Section 6.4.  Using HDL Simulation to Understand Stream Protocols

        Section 6.5.  Debugging the Generated Hardware

        Section 6.6.  Hardware Generation Notes

        Section 6.7.  Making Efficient Use of the Optimizers

        Section 6.8.  Language Constraints for Hardware Processes

        Section 6.9.  Summary

     Chapter 7.  Increasing Statement-Level Parallelism

        Section 7.1.  A Model of FPGA Computation

        Section 7.2.  C Language Semantics and Parallelism

        Section 7.3.  Exploiting Instruction-Level Parallelism

        Section 7.4.  Limiting Instruction Stages

        Section 7.5.  Unrolling Loops

        Section 7.6.  Pipelining Explained

        Section 7.7.  Summary

     Chapter 8.  Porting a Legacy Application to Impulse C

        Section 8.1.  The Triple-DES Algorithm

        Section 8.2.  Converting the Algorithm to a Streaming Model

        Section 8.3.  Performing Software Simulation

        Section 8.4.  Compiling To Hardware

        Section 8.5.  Preliminary Hardware Analysis

        Section 8.6.  Summary

     Chapter 9.  Creating an Embedded Test Bench

        Section 9.1.  A Mixed Hardware and Software Approach

        Section 9.2.  The Embedded Processor as a Test Generator

        Section 9.3.  The Role of Hardware Simulators

        Section 9.4.  Testing the Triple-DES Algorithm in Hardware

        Section 9.5.  Software Stream Macro Interfaces

        Section 9.6.  Building the Test System

        Section 9.7.  Summary

     Chapter 10.  Optimizing C for FPGA Performance

        Section 10.1.  Rethinking an Algorithm for Performance

        Section 10.2.  Refinement 1: Reducing Size by Introducing a Loop

        Section 10.3.  Refinement 2: Array Splitting

        Section 10.4.  Refinement 3: Improving Streaming Performance

        Section 10.5.  Refinement 4: Loop Unrolling

        Section 10.6.  Refinement 5: Pipelining the Main Loop

        Section 10.7.  Summary

     Chapter 11.  Describing System-Level Parallelism

        Section 11.1.  Design Overview

        Section 11.2.  Performing Desktop Simulation

        Section 11.3.  Refinement 1: Creating Parallel 8-Bit Filters

        Section 11.4.  Refinement 2: Creating a System-Level Pipeline

        Section 11.5.  Moving the Application to Hardware

        Section 11.6.  Summary

     Chapter 12.  Combining Impulse C with an Embedded Operating System

        Section 12.1.  The uClinux Operating System

        Section 12.2.  A uClinux Demonstration Project

        Section 12.3.  Summary

     Chapter 13.  Mandelbrot Image Generation

        Section 13.1.  Design Overview

        Section 13.2.  Expressing the Algorithm in C

        Section 13.3.  Creating a Fixed-Point Equivalent

        Section 13.4.  Creating a Streaming Version

        Section 13.5.  Parallelizing the Algorithm

        Section 13.6.  Future Refinements

        Section 13.7.  Summary

     Chapter 14.  The Future of FPGA Computing

        Section 14.1.  The FPGA as a High-Performance Computer

        Section 14.2.  The Future of FPGA Computing

        Section 14.3.  Summary

     Appendix A.  Getting the Most Out of Embedded FPGA Processors

        Section A.1.  FPGA Embedded Processor Overview

        Section A.2.  Peripherals and Memory Controllers

        Section A.3.  Increasing Processor Performance

        Section A.4.  Optimization Techniques That Are Not FPGA-Specific

        Section A.5.  FPGA-Specific Optimization Techniques

        Section A.6.  Summary

     Appendix B.  Creating a Custom Stream Interface

        Section B.1.  Application Overview

        Section B.2.  The DS92LV16 Serial Link for Data Streaming

        Section B.3.  Stream Interface State Machine Description

        Section B.4.  Data Transmission

        Section B.5.  Summary

     Appendix C.  Impulse C Function Reference

        CO_ARCHITECTURE_CREATE

        CO_BIT_EXTRACT

        CO_BIT_EXTRACT_U

        CO_BIT_INSERT

        CO_BIT_INSERT_U

        CO_EXECUTE

        CO_INITIALIZE

        CO_MEMORY_CREATE

        CO_MEMORY_PTR

        CO_MEMORY_READBLOCK

        CO_MEMORY_WRITEBLOCK

        CO_PAR_BREAK

        CO_PROCESS_CONFIG

        CO_PROCESS_CREATE

        CO_REGISTER_CREATE

        CO_REGISTER_GET

        CO_REGISTER_PUT

        CO_REGISTER_READ

        CO_REGISTER_WRITE

        CO_SIGNAL_CREATE

        CO_SIGNAL_POST

        CO_SIGNAL_WAIT

        CO_STREAM_CLOSE

        CO_STREAM_CREATE

        CO_STREAM_EOS

        CO_STREAM_OPEN

        CO_STREAM_READ

        CO_STREAM_READ_NB

        CO_STREAM_WRITE

        COSIM_LOGWINDOW_CREATE

        COSIM_LOGWINDOW_FWRITE

        COSIM_LOGWINDOW_INIT

        COSIM_LOGWINDOW_WRITE

     Appendix D.  Triple-DES Source Listings

        DES_HW.C

        DES.C

        DES_SW.C

        DES.H

     Appendix E.  Image Filter Listings

        IMG_HW.C

        IMG_SW.C

        IMG.H

     Appendix F.  Selected References

     Index