EMIF主要是配置672x的外部存储空间的，这是操作外设的一个必需的步骤，在此公布一下代码，使用者根据自己的SDRAM或FLASH修改一下参数即可使用。使用这缎代码勿需添加任何头文件，使用者不妨顶一下。

void InitMyEmif（void）

{

 #define EMIF_AWCCR        0xF0000004

 #define EMIF_A1CR         0xF0000010

 /* EMIF Asynchronous Wait Cycle Configuration Register */

 *(int *)EMIF_AWCCR =  ( 0 << 28) // WP0      : Insert wait cycle if AWAIT is low

      | (16 <<  0); // MEMC     : Max extended wait cycles (max = 16*(MEWC+1))

 /* EMIF global control register */

 *(int *)EMIF_A1CR =   ( 0 << 31) // SS       : Select WE mode

         | ( 1 << 30) // EW       : Enable extended wait mode

      | ( 0 << 26) // W_SETUP  :  10 ns @ 100 MHz

      | ( 9 << 20) // W_STROBE :  90 ns @ 100 MHz

      | ( 3 << 17) // W_HOLD   :  40 ns @ 100 MHz

      | ( 0 << 13) // R_SETUP  :  10 ns @ 100 MHz

      //| ( 8 <<  7) // R_STROBE :  90 ns @ 100 MHz

      | ( 9 <<  7) // R_STROBE : 100 ns @ 100 MHz

      | ( 3 <<  4) // R_HOLD   :  40 ns @ 100 MHz

      | ( 0 <<  2) // TA       :  10 ns @ 100 MHz

      | ( 1 <<  0); // ASIZE    :  16-bit data bus

 /* 2. Program AC timing registers to meet SDRAM spec */

 #define EMIF_SDCR         0xF0000008

 #define EMIF_SDRCR        0xF000000C

 #define EMIF_SDTIMR       0xF0000020

 #define EMIF_SDSRETR      0xF000003C

 /* Micron 48LC32M16A2TG-75 */

 *(int *)EMIF_SDTIMR = ( 6 << 27) // T_RFC : Auto refresh period (66ns)

      | ( 1 << 24) // T_RP  : Precharge command period (20 ns)

      | ( 1 << 20) // T_RCD : Active to read or write delay (20 ns)

      | ( 1 << 16) // T_WR  : Write recovery time (1 clk + 7.5 ns)

      | ( 4 << 12) // T_RAS : Active to precharge command (44 ns)

      | ( 6 <<  8) // T_RC  : Active to active command period (66 ns)

      | ( 1 <<  4); // T_RRD : Active bank a to active bank b command (15 ns)

 *(int *)EMIF_SDSRETR = 6; // T_RFC : Auto refresh period (66ns)

 /* 3. Program the Refresh Rate to satisfy the SDRAM power-up constraint */

 /* RR > (100 us/8) * fem_CLK = 1250 (0x4E2) */

 *(int *)EMIF_SDRCR = 0x000004E2;

 /* 4. Program the Control Register to meet SDRAM spec */

 *(int *)EMIF_SDCR =   ( 0 << 31) // SR          : To avoid self refresh state

      | ( 0 << 14) // NM          : Not narrow (32-bit)

      | ( 2 <<  9) // CL          : 2 clock

      | ( 1 <<  8) // BIT11_9LOCK : To allow the CL field to be written (legacy)

      | ( 2 <<  4) // IBANK       : 4 internal SDRAM banks

      | ( 2 <<  0); // PAGESIZE    : 1024 word pages

 /* 5. Access or wait 200 us in order to allow the EMIF

   auto-initialization sequence to complete. */

 i = *(int *)(0x80000000);

 /* 6. Program the "real" Refresh Rate to match the SDRAM refresh interval. */

 /* 64 ms, 4096 cycle refresh rate */

 /* RR <= fem_CLK * tRefreshperiod/nCycles = 1562.5

 round down to meet the "<" (0x61A) */

 *(int *)EMIF_SDRCR = 0x0000061A;

}