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| Altera AES3/EBU 参考设计 | |||||
作者：Altera 文章来源：本站 点击数： 更新时间：2007-4-5  |
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The Audio Engineering Society together with the European Broadcasting Union have developed the AES3/EBU digital audio transmission standard, a serial point-to-point interface that carries digital audio data over a standard cable. Audio data is typically in pulse code modulation (PCM) format. The AES3/EBU reference design also supports compressed audio and non-audio data transmission. The information sent over the AES3/EBU is non-return to zero (NRZ) coded with the bi-phase mark (BPM) code so clock and data can be recovered on the receive side of the interface. The AES3/EBU reference design provides both a transmitter and a receiver. The receiver extracts the data and the clock from an incoming AES3/EBU stream, and stores the parallel audio data and control bits into a FIFO buffer. The received information can be extracted from the FIFO buffer for processing, or sent directly to the transmitter. The AES3/EBU nominal data rate is directly related to the source audio sample rate. The receivers input data rate is set at compile time to a fixed frequency, supporting PCM sample rates up to 192 kHz. The transmitter takes parallel data from a FIFO buffer, performs serialization, parity bit generation, bi-phase coding, and appends the appropriate X,Y, Z header. It performs null-packet stuffing when no audio data is present in the transmit FIFO buffer. The transmit clock may be derived from an asynchronous source or it may be locked to an extracted receive clock via an external voltage-controlled crystal oscillator (VCXO). Altera supplies the AES3/EBU reference design as Verilog HDL source code. The reference design includes transmit and receive blocks, testbenches which allow testing of the Verilog HDL source code, Quartus® II implementation constraints, and demonstrations that run on Altera Stratix® GX and CycloneTM Video Demonstration Boards. If the electrical interface for Sony/Philips digital interface (S/PDIF) is adhered to, the reference design can also address the S/PDIF. For S/PDIF, some differences exist in the interpretation of the channel status block registers, but the reference design needs no changes for S/PDIF. Block Diagram Figure 1 shows the reference design block diagram.  Features AES3/EBU transmit and receive functionality Control channel status block capture on the receiver Control channel status block insertion for the transmitter Hardware cyclic redundancy check code (CRCC) checking on the receiver Hardware CRCC generation on the transmitter S/PDIF compatibility |
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