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| TI数字视频记录仪解决方案 | |||||
作者：TI 文章来源：本站 点击数： 更新时间：2007-3-18  |
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Digital Video Recorder (DVR) from Texas Instruments is a consumer video/audio product that can record and play back full-motion video/audio. Block Diagram  Design Considerations A Digital Video Recorder (DVR) is a consumer video/audio product that can record and play back full-motion video/audio using the ISO MPEG audio/video standards for the compression of video and audio content. The storage media include hard disks and recordable CD/DVD disks. Core Subsystem Includes: Analog Video Decoder - digitizes and decodes baseband analog video formats (NTSC/PAL/SECAM) into digital component video. MPEG Video CODEC/Audio Processor - performs MPEG video encoding/decoding, MPEG audio encoding/decoding, and multiplexing/demultiplexing of the audio and video bit streams. CPU - controls the DVR operating system software, overlay of text/graphics, and the user interface. Triple DAC - convertes digital video into analog video output in different formats: NTSC/PAL, S video, and YPrPb component video. The output stages require high-performance op-amps to amplify the video signals FPGA/PCI Interface - provides data/command transfer between devices connecting to the PCI bus. Stereo Audio CODEC - uses audio ADC and DAC to digitize and playback analog audio. User Interface - allows the user to control the DVR using the panel keypad or the remote control. Broadband Connectivity - allows streaming audio and video to transmit and receive through ADSL and cable modem. Power Conversion - converts the input power from the AC adaptor to run various functional blocks. A digital video recorder can be used in a variety markets, but one in particular tends to stand out the most due to recent events. TIs video surveillance solutions are based on the high performance TMS320DM64x Digital Media processors which have on chip video ports for easy connection to video devices. The DM64x family is capable of handling both video and audio encode and decode for IP based video surveillance applications. Cost-competitive video compression/decompression algorithms are available through our partner network for JPEG, MPEG2, MPEG4, H.264, and more. Audio compression/decompression algorithms are also available. DVR Platforms Table Suggested TI DSP Platforms for DVR (typical performance - preliminary).  All performance data is for 30fps YUV 4:2:0 unless otherwise noted. Note: Performance will vary depending on efficiency of code and data stream used. Resolution Information: D1(720X480)/CIF (352X288)SP=Simple Profile/ASP=Advanced Simple Profile* 33MHz 32bit** 66MHz 32bit*** TCP/IP Stack can be run on top of the Video Codecs on the DSP Application Notes H.263 Standard - Overview and TMS320C6000 DSP Implementation White Paper (spra018.htm, 9 KB) 10 Dec 2001 Abstract H.263 Encoder: TMS320C6000 Implementation (spra721.htm, 9 KB) 21 Nov 2000 Abstract H.263 Decoder: TMS320C6000 Implementation (spra703.htm, 9 KB) 13 Sep 2000 Abstract MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation (spra649.htm, 9 KB) 29 Feb 2000 Abstract |
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