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| TI基于DaVinci技术的PMP解决方案 | |||||
作者：61IC 文章来源：本站原创 点击数： 更新时间：2007-7-16  |
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Portable Media Player Based on DaVinci™Technology Today, portable media player (PMP) functionality has become a must-have for portable DTV receivers used in DVB-H/T, ISDB-T, T-DMB and VOD products. Ingenient has been at the forefront of this requirement by enabling various leading companies to introduce successful battery-powered PMPs into today’s marketplace.As a primary solution provider, Ingenient offers complete solutions that facilitate extensive digital movie, music and photo playback and recording. The MP512x-PMP-DM644x product design solution utilizes the TMS320DM644x processor based on DaVinci™ technology. This solution provides power-efficient, high-quality multimedia, giving Ingenient’s customers the capability to make highend digital media products without sacrificing portability or power. The solution also includes TI AIC33 stereo codec, TVP5160 video decoder and TPS62/TPS76 series power regulations. 下图为PMP方框图:  功能描述: User-friendly graphical interface for easy operation Record video and synchronized audio directly from TV, VCR, DVD player or video camera plus still images Record audio directly from any stereo or mono audio source including microphone Download and store digital video, audio and images from PC over USB 2.0 or 802.11 b/g Play movies on an integral LCD screen and headphones or on a TV monitor and speakers Display photos with or without music in still or Photo Show mode View and record DVB-H, T-DMB or ISDB-T broadcast content Personal navigation and broadcast content viewing. 所选用的元件: TMS320DM644x processor TLV320AIC33 (audio codec) TVP5160 (video codec) TPS62xxx (power regulators) TPS76xxx (power regulators) 开发板: MP4900-BRD-DM644x-10 Schematics Gerber files 软件: Multimedia framework Integrated multimedia operational modes and functions Operating systems WinCE 5.0 Linux 2.6.15 Video pre/post processing Audio equalization and audio post processing Audio/video/communications hardware drivers AIC33 TVP5160 USB 2.0 Host/Client LAN 802.11g Video codecs H.264 MPEG4 SP/ASP MPEG2 MPEG1 DivX (home theater profile) XviD Windows Media® Video 7/8/9 Audio codecs Dolby digital (AC-3) MPEG2 AAC LC MPEG4 AAC LC MPEG4 AAC HE (version 1.0 and 2.0) MPEG1/2 layer 1 and 2 MPEG1/2 layer 3 (including MP3 2.5) Windows Media® Audio Ogg Vorbis Speech codecs G.711 G.722/722.1 G.723.1 G.726 G.729AB GSM-AMR 人门文件: API manuals User guides Example code Release notes Email/phone support Ingenient Services Integration Customization Solution design 下面是TMS320DM6443的性能介绍: The TMS320DM6443 (also referenced as DM6443) leverages TIs Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The TMS320C64x+ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000 DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: 1 configurable video port; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6443 includes a Video Processing Sub-System (VPSS) that has a configurable Resizer and Video Processing Back-End (VPBE) output used for display. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644X MPU core processor and the network. The DM6443 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the MPU, the DIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the MPU, allowing the MPU to poll the link status of the device without continuously performing costly MDIO accesses. The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6443 to easily control peripheral devices and/or communicate with host processors. The DM6443 also provides multimedia card support, MMC/SD, with SDIO support. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6443 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.  |
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