TMS320C6000 Expansion Bus Host Port Performance Zoran Nikolic Digital Signal Processing Solutions ABSTRACT The expansion bus is a 32-bit wide bus that supports interfaces to PCI bridge chips, to synchronous or asynchronous external masters, to a variety of asynchronous peripherals, and to asynchronous or synchronous FIFOs. The expansion bus has two major subblocks—the I/O port and host port Interface. This application report discusses performance of the TMS320C6000E expansion bus host port. The expansion bus host port performance is described here using: • The maximum data throughput (in Mbytes/s), • Number of clocks required to perform a transfer and, • Latencies required to start and complete a transfer. System performance is affected by a variety of factors including: • The DMA auxiliary channel (which performs expansion bus transfers) competes for control of the DMA with other DMA channels. • DMA controller competes with the CPU for resources (external memory interface (EMIF), internal memory). • If the resource accessed is within the EMIF it is susceptible to stalls such as SDRAM page misses, and asynchronous not ready conditions. Many of these factors are within the system designer’s control. This application note basses on best case performance to give the system designer an idea of the upper band of available bandwidth. The performance was evaluated using the VHDL simulation. =====================================================================
