2021-10-17 21:22:40 索炜达电子 378
项目编号:E1550
文件大小:278K
源码说明:带中文注释
开发环境:VHDL
简要概述:
基于FPGA FIR多功能滤波器设计
目录│文件列表:
└ FPGA-FIR-Filter
├ Docs
│ │ FPGA_Vision_Experiments_FIR-Filter.pdf
│ └ FPGA_Vision_Experiments_FIR-Filter.pptx
├ FPGA-Design
│ │ sharp.sdc
│ │ sharp.vhd
│ │ sharp_arith.vhd
│ │ sharp_control.vhd
│ │ sharp_default_Cyclone_IV.qsf
│ │ sharp_default_Cyclone_V.qsf
│ │ sharp_linemem.vhd
│ └ sharp_slice.vhd
├ Octave
│ │ sharp_filter_coefficients.m
│ │ sharp_frequency_response.m
│ └ sharp_image_filter.m
└ Verification
│ sharp_generate_testbench_images.m
│ sim_sharp.vhd
│ sim_sharp_self-checking.vhd
└ write_ascii_ppm.m